1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly to nonvolatile semiconductor memory that is programmable as well as erasable.
2. Description of the Related Art
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. Some types of nonvolatile memory are capable of being repeatedly programmed and erased, including erasable programmable read only semiconductor memory generally known as EPROM, and electrically erasable programmable read only semiconductor memory generally known as EEPROM. EPROM memory is erased by application of ultraviolet light and programmed by application of various voltages, while EEPROM memory is both erased and programmed by application of various voltages. EPROMs and EEPROMs have suitable structures, generally known as floating gates, that are charged or discharged in accordance with data to be stored thereon. The charge on the floating gate establishes the threshold voltage, or VT, of the device, which is sensed when the memory is read to determine the data stored therein.
An illustrative well known type of compact floating gate EEPROM cell structure is the stacked gate structure shown in FIG. 1. A floating gate 14, typically a doped polysilicon layer, is sandwiched between two insulator layers 12 and 16, typically oxide. The top layer of the stack is a control gate electrode 10, typically a doped polysilicon layer. The stacked gate structure is shown symmetrically overlying part of a heavily doped n+ source region 20 and a heavily doped n+ drain region 22, as well as a channel region between the source region 20 and the drain region 22. The channel region is part of a p-well 28, which also contains the source region 20, the drain region 22, and a heavily p+ doped contact region 24. The p-well 28 typically is contained within an n-type substrate or within an n-well such as shown at 30, which also contains a heavily n+ doped contact region 26. The n-well 30 is in turn contained in the p-type substrate 32. Many variations in the floating gate EEPROM cell structure are known, and include asymmetrical stacked gate structures, split gate structures, and so forth. Moreover, although the structure of FIG. 1 is an n-channel enhancement mode device, nonvolatile memory cells may be fabricated as either n-channel or p-channel devices or as enhancement or depletion mode devices.
As is typical of nonvolatile memory cells that are capable of being repeatedly programmed and erased, the various functions of the EEPROM stacked gate memory cell of FIG. 1 are controlled by applying various bias voltages. The voltage applied to the control gate is VG, the voltage applied to the source is VS, the voltage applied to the drain is VD, the voltage applied to the p-well 28 is VP, the voltage applied to the n-well 30 is VN, and the voltage applied to the p-type substrate 32 is VB (not shown). Typically the substrate 32 is grounded, i.e. VB=0V. Typically writing or programming the memory cell means adding negative charge to the floating gate while erasing the memory cell means removing negative charge from the floating gate, but the charged state can be considered the erased state if desired. Other voltages are applied to read the charge state of the memory cell by detecting the threshold voltage VT of the memory cell, which ideally is done without disturbing the charge state.
Depending to some extent on device characteristics, the stacked gate transistor of FIG. 1 may be programmed by moving electrons to the floating gate 16 using Fowler-Nordheim (xe2x80x9cFNxe2x80x9d) tunneling or electron injection. Electron injection typically is done using channel hot electron injection (xe2x80x9cCHExe2x80x9d) or channel-initiated secondary electron injection (xe2x80x9cCISEIxe2x80x9d).
The EEPROM stacked gate memory cell of FIG. 1 may be used in a variety of memory array architectures, including common ground arrays as well as virtual ground arrays. A memory is formed by combining a memory array with well known circuitry such as control logic, address decoders, sense amplifiers, and power supplies. An example of a memory 40 having an flash memory array 54 of such individual cells is shown in FIG. 2. Various read, erase and program voltages are furnished by suitable power supplies (not shown). A serial memory address ADDR is latched into an address latch 44, decoded for its row and column information (X and Y) by X decoder 48 and Y decoder 46, and applied to the memory array 54 to access the selected row and column. If the operation is a program operation, the data to be written is temporarily stored in I/O buffer 50 as it is written to the memory array 54. If the operation is a read, the selected bits are sensed by sense amplifier 52 and then temporarily stored in the I/O buffer 50, where they are accessible to external circuits.
For many memory applications, one desires to read and program multiple bytes of the memory array 54 simultaneously, or even an entire page of the memory array 54. Similarly, one may desire to erase multiple bytes or even an entire page of the memory array 54 at one time, or even multiple pages or the entire memory. To facilitate erasing, programming and reading multiple bytes or even an entire page, each row of the memory array or perhaps adjacent rows may correspond to a page of memory. A sector of memory may contain several pages. Such memory is known as xe2x80x9cflashxe2x80x9d memory because of the large number of bits that can be erased or programmed simultaneously.
One type of conventional flash memory uses FN tunneling for both erasure and programming. Unfortunately, programming using FN tunneling from the drain edge to the floating gate is relatively slow. Transistors using FN programming generally requires a longer channel length, leading to larger cell size. FN programmed memories also require bit-latch circuitry, which increases the size of the memory chip.
Another type of conventional flash memory uses CHE for programming. CHE programming is fast relative to FN programming. Unfortunately, the high drain voltage and programming current required by CHE renders the technique disadvantageous for use in low power applications, and severely limits the number of bits that can be programmed at one time. Simultaneous multiple byte programming is difficult to perform, as a practical matter.
While multiple byte programming and page mode programming of a CHE type memory can be achieved by repeated programming groups of bits until the desired amount of memory is programmed, the approach can result in an unfavorable condition known as program-disturb. Program-disturb is related to the voltage conditions that occur in the part of the memory that is not being programmed while another part of the memory is being programmed. These voltage conditions cause multiple minute shifts in the threshold voltage of the memory cells that are not being programmed, which occur as other parts of the memory are being programmed. A similar problem occurs during read-out of data. Read voltages applied to the nonvolatile cells, including both the addressed cells and some of the cells that are not addressed, can induce a threshold voltage shift in these cells. While program-disturb and read-disturb can be avoided by the use of an isolating select transistor in each memory cell, such transistors are undesirable insofar as they cause an increase in the size of the memory cell and a corresponding decrease in the memory array density.
A technique is known that uses negative substrate biasing of the flash memory cells to overcome some of the disadvantages of conventional CHE. An example of this technique is disclosed in U.S. Pat. No. 5,659,504, which issued Aug. 19, 1997, to Bude et al. and is entitled xe2x80x9cMethod and Apparatus for Hot Carrier Injection.xe2x80x9d The Bude et al. programming technique, which is referred to as channel-initiated secondary electron injection (xe2x80x9cCISEIxe2x80x9d), uses a positive bias voltage of about 1.1 volts to about 3.3 volts at the drain and a negative bias voltage of about xe2x88x920.5 volts or more negative at the substrate, with the source at zero volts. The source-drain voltage causes some channel hot electron generation while the substrate bias promotes the generation of a sufficient amount of secondary hot electrons having a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate. The secondary hot electrons are primarily involved in charging the floating gate. The programming of the flash memory array using CISEI transistors is relatively quickly achieved with low programming current, low drain voltage, and smaller cell size (shorter channel length) relative to flash memory arrays using CHE transistors. However, simultaneous multiple byte programming and page mode programming are still difficult to achieve. Unfortunately, as in the case the CHE memory array, the use of isolating select transistors in CISEI memory cells increases their size, and the technique of repeated programming groups of bits until the desired amount of memory is programmed can cause program-disturb.
While CHE and CISEI cell programming is faster that FN cell programming, multiple byte programming and page mode programming of CHE and CISEI memory arrays remains problematical. FN tunneling remains a popular choice in flash memory for erase operations.
We have found that flash memory suffers disturbance of the floating gate potential especially during page mode programming operations, and may also suffer disturbance of the floating gate potential during read operations. We have also found that the relatively thin high quality tunnel oxide commonly found in EEPROM memory cells has a shortened lifetime because of the high fields that occur across the tunnel oxide during the FN erase operations.
These and other disadvantages are overcome individually or collectively in various embodiments of the present invention. For example, one embodiment of the present invention is a method of programming a memory array that comprises a plurality of memory cells coupled to a plurality of word select lines, each of the memory cells having an adjustable threshold voltage and a gate overlying a channel and being programmable using channel hot electron injection. The method comprises applying a first voltage to the channels; establishing a voltage differential across the respective channels of at least a first and a second of the memory cells, the potential differential being sufficient to generate channel hot electrons in the respective channels thereof; applying a second voltage to the gate of the first memory cell, the second voltage having a polarity and magnitude relative to the first voltage sufficient to attract the hot electrons and change the threshold voltage of the first memory cell to a programmed state; and applying a third voltage to the gate of the second memory cell, the third voltage having a polarity and magnitude relative to the first voltage sufficient to repel the hot electrons and deter change in the threshold voltage of the second memory cell.
Yet another embodiment of the present invention is a NOR-type memory integrated circuit comprising a plurality of word select lines; a plurality of bit lines; a plurality of source lines; a memory array having a plurality of adjustable threshold voltage memory transistors, each being programmable using channel hot electron injection and having a source coupled to one of the source lines, a drain coupled to one of the bit lines, a floating gate overlying a channel defined in a substrate body region between the source and the drain, and a control gate overlying the floating gate and coupled to one of the word select lines; a voltage source for applying a body voltage to the substrate body regions containing the channels; a voltage source for applying a source voltage to the sources of at least a first and a second of the memory transistors via a common one of the source lines; a voltage source for applying a drain programming voltage to the drains of the first and second memory transistors via a common one of the column lines, the source and drain programming voltages being sufficient to generate channel hot electrons in the respective channels of the first and second memory transistors; a voltage source for applying a select voltage to the gate of the first memory transistor via a first one of the word select lines, the select voltage having a polarity and magnitude relative to the body voltage sufficient to attract the hot electrons of the first memory transistor and change the threshold voltage thereof to a programmed state; and a voltage source for applying an unselect voltage to the gate of the second memory cell via a second one of the word select lines, the unselect voltage having a polarity and magnitude relative to the first voltage sufficient to repel the hot electrons of the second memory transistor and deter change in the threshold voltage thereof.
Another embodiment of the present invention is a virtual ground-type memory integrated circuit comprising a plurality of word select lines; a plurality of column lines; a memory array having a plurality of adjustable threshold voltage memory transistors, each being programmable using channel hot electron injection and having a source coupled to one of the column lines, a drain coupled to an adjacent one of the column lines, a floating gate overlying a channel defined in a substrate body region between the source and the drain, and a control gate overlying the floating gate and coupled to one of the word select lines; a voltage source for applying a body voltage to the substrate body regions containing the channels; a voltage source for applying a reference voltage to the sources of at least a first and a second of the memory transistors via a first one of the column lines; a voltage source for applying a programming voltage to the drains of the first and second memory transistors via a second one of the column lines adjacent the first column line, the reference and programming voltages being sufficient to generate channel hot electrons in the respective channels of the first and second memory transistors; a voltage source for applying a select voltage to the gate of the first memory transistor via a first one of the word select lines, the select voltage having a polarity and magnitude relative to the body voltage sufficient to attract the hot electrons of the first memory transistor and change the threshold voltage thereof to a programmed state; and a voltage source for applying an unselect voltage to the gate of the second memory cell via a second one of the word select lines, the unselect voltage having a polarity and magnitude relative to the first voltage sufficient to repel the hot electrons of the second memory transistor and deter change in the threshold voltage thereof.